Job Details

Skills and Responsibilities:

1. ASIC/IP RTL to Emulation platforms (Preferred: Zebu, Palladium)
2. Build model from released RTL
3. Generate target platform loadable image(s), test and release the image to Firmware and DV teams.
4. Run sanity tests for qualifying release of the image(s)
5. Release the model to various teams including Functional Validation team, Firmware, DV
6. Assist debug of failures providing instrumented model (Waveform Dumps, in circuit debug) and interfacing with stakeholders.
7. Coordinate with Tools team to validate tool and Model release
8. FPGA and Emulator flows and methodologies
9. Experience with Daughtercards, Speedbridges, Virtual Prototyping
10. Hardware emulators, such as Zebu is a must have, Palladium is appreciated
11. Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration
12. Strong knowledge of Complete Design Cycle to understand the Different IP designs to integrate In the build
13. Simulation acceleration knowledge (DPI and Transactors)
14. In depth understanding of RTL and Synthesis
15. Logic simulation: VCS/NCSIM
16. Programming/scripting skills (C, C++, Python)
17. Experience with CPU integration is a big plus, especially ARM/RISC-V CPU
18. Knowledge of CoreSight/UltraSoC debug infrastructure integration is a plus
19. Knowledge of OS kernel and experience in driver development
20. Experience with FPGA and/or Emulation platforms
21. Experience with lab system debug with logic analyzers, scopes, meters etc.

Additional Skills:

1. PROTOTYPE
2. SELF MOTIVATED
3. STRUCTURED SOFTWARE
4. PROTOTYPING
5. PYTHON
6. SCRIPTING
7. SOC
8. TCL
9. USB
10. ALGORITHM
11. ARCHITECTURE
12. DEBUG
13. FIELD PROGRAMMABLE GATE ARRAY
14. FIRMWARE
15. LOGIC ANALYZERS
16. PCI EXPRESS
17. PERFORMANCE MODELING

Additional Job Details: 1 - Concept Prototyping (P3 - Advanced) | 2 - Firmware Engineering (P3 - Advanced)

Primary Skill: Python